1. Field of the Invention
This invention relates in general to a decoding system and method, and more particularly to a decoding system and method in an optical disk storage device with high decoding speed by decreasing the access times to a data buffer.
2. Description of the Related Art
Referring now to FIG. 1, it is a block diagram of a conventional decoding system in a DVD storage device. As shown in FIG. 1, a demodulator 102 reads the data stored in the disk 100 for converting 16 bit code words into 8 bit data symbols. Then, the demodulator 102 generates an ECC(Error Correction Code) block 107 and transmits the ECC block 107 to a data buffer 106 through a bus 104. The ECC block 107 comprises main data 108, a PO(parity of outer-code) 110 and a PI(parity of inner-code) 112. The scale of the main data 108 is 192*172 bytes, the scale of the PO 110 is 16*172 bytes, and the scale of the PI 112 is 208*10 bytes. Main data 108 appended with the PO 110 forms an outer-code of RS(Reed Solomon), and main data 108 appended with the PO 110 and the PI 112 forms an inner-code of RS. ECC decoder 114 reads the ECC block 107 from the data buffer 106 to perform the error correction decoding along the PI direction (i.e. X direction) and PO direction (i.e. Y direction) of the ECC block 107 in turn. Then, the ECC decoder 114 writes the corrected part of the ECC block 107 into the data buffer 106. The de-scrambler and EDC(Error Detection Code)check 116 reads the corrected main data 108 stored in the data buffer 106 for de-scrambling the main data 108 and checking whether errors in the main data 108 are corrected. When the host needs the main data 108, an ATAPI(Advanced Technology Attachment Packet Interface) 118 reads the main data 108 in the data buffer 106, then de-scrambles and transmits the main data 108 to the host.
Referring to FIG. 2, it illustrates a flow chart of the conventional decoding system accessing to the data buffer in a DVD storage device. At a step 201, after performing demodulation, a demodulator 102 writes an ECC block 107 into a data buffer 106. Next, at a step 202, an ECC decoder 114 reads the ECC block 107 of the PI direction to perform the error correction decoding, then writes the corrected part of the ECC block 107 into the data buffer 106. Continuing the step 202, it flows to a step 203, the ECC decoder 114 reads the ECC block 107 of the PO direction to perform the error correction decoding, then writes the corrected part of the ECC block 107 into the data buffer 106. After finishing the step 203, the system can repeat the steps 202 and 203 to enhance the error correction capability according to the setting of the system. Then at a step 204, the de-scrambler and EDC check 116 reads the corrected main data 108 stored in the data buffer 106 for de-scrambling the main data 108 and checking whether errors in the main data 108 are corrected. When the host needs the main data 108, at a step 205, an ATAPI 118 reads the main data 108 stored in the data buffer 106, then de-scrambles and transmits the main data 108 to the host. In the preceding prior art, each module of the decoding system needs to run the above-mentioned steps in turn to finish the decoding process in a DVD storage device.
Referring now to FIG. 3, it illustrates a flow chart of decoding RS code in a conventional ECC decoder. At a stage 301, original code words in the data buffer 106 enter the stage of syndrome generation, wherein the ECC decoder 114 calculates the PI syndrome or the PO syndrome. Next, at a stage 302, the ECC decoder 114 calculates the “erasure location polynomial” according to the known erasure location, then calculates the “Fomey's modified syndrome polynomial” and gets the initial value of the next stage according to the calculated syndromes and erasure location polynomial. Continuing the stage 302, at a stage 303, the ECC decoder 114 calculates the “error-erasure locator polynomial” and “error erasure evaluator polynomial” according to the initial value produced by the previous stage 302. Then, at a stage 304, a Chien search unit finds the error locations and error magnitudes. Finally, at a stage 305, the ECC decoder 114 corrects the errors in the original code words to get the correct code words and writes them into the data buffer 106.
According to FIG. 1, when the conventional decoding system performs the decoding process, each module of the system needs to access to the data buffer. If each module of the decoding system can access to the data buffer synchronously, the system can increase the decoding speed to become a high speed DVD. However, according to FIGS. 2 and 3 the ECC decoder 114 in the conventional decoding system must access to the data buffer when it performs the error correction decoding along the PI and PO directions of the ECC block each time, thereby it takes a lot of time and limits the speed of the entire DVD system for many accesses to the data buffer. Now there are several solutions for the above bottleneck: enhancing the clock frequency of the decoding system, increasing the bus width of the decoding system, and decreasing the access times to the data buffer, etc.